Datasheet

Rev.6.00 Mar. 18, 2009 Page xlii of lviii
REJ09B0050-0600
Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0)......................................................................... 199
Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ....................................................... 200
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode ................................... 203
Figure 6.55 Example of Timing when Write Data Buffer Function is Used ............................. 205
Figure 6.56 Bus Released State Transition Timing ................................................................... 208
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ...................................................................................... 214
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................ 239
Figure 7.3 Operation in Sequential Mode................................................................................ 247
Figure 7.4 Example of Sequential Mode Setting Procedure.................................................... 248
Figure 7.5 Operation in Idle Mode .......................................................................................... 249
Figure 7.6 Example of Idle Mode Setting Procedure .............................................................. 251
Figure 7.7 Operation in Repeat mode...................................................................................... 254
Figure 7.8 Example of Repeat Mode Setting Procedure.......................................................... 255
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)............ 257
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode is Specified).................................................................... 258
Figure 7.11 Operation in Normal Mode .................................................................................... 260
Figure 7.12 Example of Normal Mode Setting Procedure......................................................... 261
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)................................................ 263
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)................................................ 264
Figure 7.15 Operation Flow in Block Transfer Mode ............................................................... 265
Figure 7.16 Example of Block Transfer Mode Setting Procedure............................................. 266
Figure 7.17 Example of DMA Transfer Bus Timing................................................................. 267
Figure 7.18 Example of Short Address Mode Transfer............................................................. 268
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) ......................................... 269
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)......................................... 270
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) ......................... 271
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................ 272
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer.... 273
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer................... 274
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer....... 275
Figure 7.26 Example of Single Address Mode Transfer (Byte Read) ....................................... 276
Figure 7.27 Example of Single Address Mode (Word Read) Transfer...................................... 276
Figure 7.28 Example of Single Address Mode Transfer (Byte Write) ...................................... 277
Figure 7.29 Example of Single Address Mode Transfer (Word Write)..................................... 278