Datasheet

Rev.6.00 Mar. 18, 2009 Page xl of lviii
REJ09B0050-0600
Figure 3.14 H8S/2365 Memory Map (2)................................................................................... 76
Figure 3.15 H8S/2363 Memory Map......................................................................................... 77
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled).......................... 82
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)......................... 83
Figure 4.3 Stack Status after Exception Handling................................................................... 86
Figure 4.4 Operation when SP Value Is Odd........................................................................... 87
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller................................................................... 90
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0......................................................... 102
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0 ................................................................................... 109
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2 ................................................................................... 111
Figure 5.5 Interrupt Exception Handling................................................................................. 113
Figure 5.6 Contention between Interrupt Generation and Disabling ....................................... 116
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller .......................................................................... 120
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)....................... 129
Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0) ....................................................................................................... 131
Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................ 139
Figure 6.5 Area Divisions........................................................................................................ 145
Figure 6.6 CSn Signal Output Timing (n = 0 to 7) .................................................................. 150
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space) .......................... 151
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space)......................... 151
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space .......................................................... 153
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space .......................................................... 154
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access).......... 155
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)........... 156
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ............................... 157
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access).......... 158
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)........... 159
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ............................... 160
Figure 6.17 Example of Wait State Insertion Timing................................................................ 162
Figure 6.18 Example of Read Strobe Timing............................................................................ 163