Datasheet

Rev.6.00 Mar. 18, 2009 Page xxxix of lviii
REJ09B0050-0600
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2367F, H8S/2365, and H8S/2363........................ 3
Figure 1.2 Internal Block Diagram of H8S/2368 0.18 μm F-ZTAT Group............................. 4
Figure 1.3 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363.................................. 5
Figure 1.4 Pin Arrangement of H8S/2368 0.18 μm F-ZTAT Group....................................... 6
Figure 1.5 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363.................................. 7
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)................................................................ 25
Figure 2.2 Stack Structure in Normal Mode............................................................................ 25
Figure 2.3 Exception Vector Table (Advanced Mode)............................................................ 26
Figure 2.4 Stack Structure in Advanced Mode........................................................................ 27
Figure 2.5 Memory Map.......................................................................................................... 28
Figure 2.6 CPU Internal Registers........................................................................................... 29
Figure 2.7 Usage of General Registers .................................................................................... 30
Figure 2.8 Stack....................................................................................................................... 31
Figure 2.9 General Register Data Formats (1)......................................................................... 34
Figure 2.9 General Register Data Formats (2)......................................................................... 35
Figure 2.10 Memory Data Formats............................................................................................ 36
Figure 2.11 Instruction Formats (Examples) ............................................................................. 48
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode................... 52
Figure 2.13 State Transitions..................................................................................................... 56
Section 3 MCU Operating Modes
Figure 3.1 H8S/2368F Memory Map (1)................................................................................. 63
Figure 3.2 H8S/2368F Memory Map (2)................................................................................. 64
Figure 3.3 H8S/2367F Memory Map (1)................................................................................. 65
Figure 3.4 H8S/2367F Memory Map (2)................................................................................. 66
Figure 3.5 H8S/2364F Memory Map (1)................................................................................. 67
Figure 3.6 H8S/2364F Memory Map (2)................................................................................. 68
Figure 3.7 H8S/2362F Memory Map (1)................................................................................. 69
Figure 3.8 H8S/2362F Memory Map (2)................................................................................. 70
Figure 3.9 H8S/2361F Memory Map (1)................................................................................. 71
Figure 3.10 H8S/2361F Memory Map (2)................................................................................. 72
Figure 3.11 H8S/2360F Memory Map (1)................................................................................. 73
Figure 3.12 H8S/2360F Memory Map (2)................................................................................. 74
Figure 3.13 H8S/2365 Memory Map (1) ................................................................................... 75