Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 346 of 980
REJ09B0050-0600
• P20/PO0/TIOCA3/TMRI0
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, and bit P20DDR.
TPU channel 3
settings
(1) in table below (2) in table below
P20DDR — 0 1 1
NDER0 — — 0 1
P20 input P20 output PO0 output TIOCA3 output
TIOCA0 input
*
1
Pin function
TMRI0 input
*
2
Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××.
2. When used as the TMR counter reset pin, set both the CCLR1 and CCLR0 bits in
TCR_1 to 1.
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001× B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00 Other than
B'××00
Other than
B'××00
CCLR2 to
CCLR0
— — — — Other than
B'001
B'001
Output function — Output
compare
output
— PWM
*
3
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 3. TIOCB3 output disabled.