Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 341 of 980
REJ09B0050-0600
• P25/PO5/TIOCB4/TMO1
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bits OS3 to USO in TCSRI
of TMR.
TPU channel 4
settings
(1) in table below (2) in table below
OS3 to OS0 — All 0 All 1 One value is 1
P25DDR — 0 1 1 —
NDER5 — — 0 1 —
P25 input P25 output PO5 output TMO1 output Pin function TIOCB4 output
TIOCB4 input
*
Note: * TIOCB4 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
TPU channel 4
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 to B'01×× B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
— B'××00 Other than B'××00
CCLR1, CCLR0 — — — — Other than
B'10
B'10
Output function — Output
compare
output
— — PWM mode
2 output
—
Legend:
×: Don’t care