Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 340 of 980
REJ09B0050-0600
• P26/PO6/TIOCA5
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL, and bit P26DDR.
TPU channel 5
settings
(1) in table below (2) in table below
P26DDR — 0 1 1
NDER6 — — 0 1
P26 input P26 output PO6 output Pin function TIOCA5 output
TIOCA5 input
*
1
Note: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
TPU channel 5
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 to B'00×× B'001× B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00 Other than
B'××00
Other than B'××00
CCLR1, CCLR0 — — — — Other than
B'01
B'01
Output function — Output
compare
output
— PWM
*
2
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 2. TIOCB5 output disabled.