Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 339 of 980
REJ09B0050-0600
9.2.4 Pin Functions
Port 2 pins also function as PPG outputs, TPU I/Os, and TMR I/Os. The correspondence between
the register specification and the pin functions is shown below.
• P27/PO7/TIOCB5
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL, and bit P27DDR.
TPU channel 5
settings
(1) in table below (2) in table below
P27DDR — 0 1 1
NDER7 — — 0 1
P27 input P27 output PO7 output Pin function TIOCB5 output
TIOCB5 input
*
Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1.
TPU channel 5
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 to B'01×× B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
— B'××00 Other than B'××00
CCLR1, CCLR0 — — — — Other than
B'10
B'10
Output function — Output
compare
output
— — PWM mode
2 output
—
Legend:
×: Don’t care