Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 331 of 980
REJ09B0050-0600
• P15/PO13/TIOCB1/TCLKC/DACK1
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit
NDER13 in NDERH, bit SAE1 in DMA BCRH and bit P15DDR.
SAE1 0 1 1
TPU channel 2
settings
(1) in table below (2) in table below —
P15DDR — 0 1 1 —
NDER13 — — 0 1 —
P15
input
P15 output PO13 output TIOCB1 output
TIOCB1 input
*
1
DACK1
output
Pin function
TCLKC input
*
2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101.
TCLKC input when phase counting mode is set for channels 2 and 4.
TPU channel 1
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01×× B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
— B'××00 Other than B'××00
CCLR1, CCLR0 — — — — Other than
B'10
B'10
Output function — Output
compare
output
— — PWM mode
2 output
—
Legend:
×: Don’t care