Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 329 of 980
REJ09B0050-0600
9.1.4 Pin Functions
Port 1 pins also function as the pins for PPG outputs, TPU I/Os, and DMAC outputs. The
correspondence between the register specification and the pin functions is shown below.
• P17/PO15/TIOCB2/TCLKD
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in
NDERH, and bit P17DDR.
TPU channel 2
settings
(1) in table below (2) in table below
P17DDR — 0 1 1
NDER15 — — 0 1
P17 input P17 output PO15 output TIOCB2 output
TIOCB2 input
*
1
Pin function
TCLKD input
*
2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
TPU channel 2
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01×× B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
— B'××00 Other than B'××00
CCLR1, CCLR0 — — — — Other than
B'10
B'10
Output function — Output
compare
output
— — PWM mode
2 output
—
Legend:
×: Don’t care