Datasheet

Section 8 Data Transfer Controller (DTC)
Rev.6.00 Mar. 18, 2009 Page 299 of 980
REJ09B0050-0600
8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG)
DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer
has ended
• When the specified number of transfers have
ended
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of
transfers have not ended
• When 0 is written to the DTCE bit after reading
DTCE = 1