Datasheet

Section 8 Data Transfer Controller (DTC)
Rev.6.00 Mar. 18, 2009 Page 297 of 980
REJ09B0050-0600
8.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined − DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 8.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers,
clearing of the activation source flag, and clearing of
DTCER is not performed.
6 DISEL Undefined − DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5 CHNS Undefined − DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4
to
0
− Undefined − Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
8.2.3 DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4 DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.