Datasheet
Section 8 Data Transfer Controller (DTC)
Rev.6.00 Mar. 18, 2009 Page 294 of 980
REJ09B0050-0600
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA
CRB
DAR
SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG:
DTVECR:
DTCERA
to
DTCERG
DTVECR
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G
DTC vector register
Figure 8.1 Block Diagram of DTC