Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 291 of 980
REJ09B0050-0600
φ
Internal address
Internal read signal
External address
HWR, LWR
Internal write signal
TEND
Not output
DMA
read
External write by CPU, etc.
DMA
write
Figure 7.41 Example in which Low Level is Not Output at TEND Pin
7.7.5 Activation by Falling Edge on DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
7.7.6 Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request
is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before write to DMABCRL to enable transfer.