Datasheet

Rev.6.00 Mar. 18, 2009 Page xxxiii of lviii
REJ09B0050-0600
14.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 602
14.7 Operation in Smart Card Interface Mode.......................................................................... 604
14.7.1 Pin Connection Example...................................................................................... 604
14.7.2 Data Format (Except for Block Transfer Mode).................................................. 605
14.7.3 Block Transfer Mode ........................................................................................... 606
14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 606
14.7.5 Initialization ......................................................................................................... 608
14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 608
14.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 612
14.7.8 Clock Output Control........................................................................................... 613
14.8 IrDA Operation ................................................................................................................. 616
14.9 SCI Interrupts.................................................................................................................... 619
14.9.1 Interrupts in Normal Serial Communication Interface Mode............................... 619
14.9.2 Interrupts in Smart Card Interface Mode ............................................................. 621
14.10 Usage Notes ...................................................................................................................... 622
14.10.1 Module Stop Mode Setting .................................................................................. 622
14.10.2 Break Detection and Processing........................................................................... 622
14.10.3 Mark State and Break Sending............................................................................. 622
14.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only)..................................................................... 623
14.10.5 Relation between Writes to TDR and the TDRE Flag ......................................... 623
14.10.6 Restrictions on Use of DMAC or DTC................................................................ 623
14.10.7 Operation in Case of Mode Transition................................................................. 624
Section 15 I
2
C Bus Interface2 (IIC2) (Option)............................................................ 629
15.1 Features............................................................................................................................. 629
15.2 Input/Output Pins .............................................................................................................. 631
15.3 Register Descriptions ........................................................................................................ 632
15.3.1 I
2
C Bus Control Register A (ICCRA) .................................................................. 633
15.3.2 I
2
C Bus Control Register B (ICCRB)................................................................... 635
15.3.3 I
2
C Bus Mode Register (ICMR)........................................................................... 636
15.3.4 I
2
C Bus Interrupt Enable Register (ICIER) .......................................................... 637
15.3.5 I
2
C Bus Status Register (ICSR)............................................................................ 639
15.3.6 Slave Address Register (SAR)............................................................................. 641
15.3.7 I
2
C Bus Transmit Data Register (ICDRT)............................................................ 642
15.3.8 I
2
C Bus Receive Data Register (ICDRR)............................................................. 642
15.3.9 I
2
C Bus Shift Register (ICDRS)........................................................................... 642
15.4 Operation........................................................................................................................... 643
15.4.1 I
2
C Bus Format..................................................................................................... 643