Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 289 of 980
REJ09B0050-0600
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
[2]
[1]
Note: The lower word of MAR is the updated value after the operation in [1].
CPU longword read
DMA transfer cycle
MAR upper
word read
MAR lower
word read
DMA read
DMA write
DMA internal
address
DMA control
DMA register
operation
Transfe
source
Transfer
destination
Idle
Read
Write
Idle
Figure 7.40 Contention between DMAC Register Update and CPU Read
7.7.2 Module Stop
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
7.7.3 Write Data Buffer Function
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, external write cycles in dual address transfers or single address transfers are executed in
parallel with internal accesses (on-chip memory or internal I/O registers).