Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 284 of 980
REJ09B0050-0600
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle or external bus release cycle.
7.5.14 DMAC and NMI Interrupts
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are
set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1
again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an
NMI interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
Set DTME bit to 1
Transfer continues
[1]
[2]
DTE = 1
DTME = 0
Transfer ends
No
Yes
[1]
[2]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
Write 1 to the DTME bit.
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt