Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 283 of 980
REJ09B0050-0600
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read DMA write DMA read DMA write DMA read DMA write
DMA
read
φ
Address bus
RD
HWR
LWR
DMA control
Channel 0A
Channel 0B
Channel 1
Idle Write
Idle Read Write Idle Read Write Read
Request
hold
Request
hold
Bus
release
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Channel 1 transfer
Bus
release
Request
hold
Read
Selection
Non-
selection
Selection
Request clear
Request clear
Request clear
Figure 7.34 Example of Multi-Channel Transfer
7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles
When the DMAC accesses external space, conflict with a refresh cycle or external bus release
cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle
or external bus release cycle, in accordance with the external bus priority order, even if the DMAC
is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has
a lower priority than the DMAC, is not executed until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.