Datasheet
Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 278 of 980
REJ09B0050-0600
DMA write
φ
Address bus
DMA write DMA write
DMA
dead
HWR
TEND
DACK
Bus
release
LWR
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.