Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 269 of 980
REJ09B0050-0600
DMA
read
φ
Address bus
RD
LWR
TEND
HWR
Bus release Last transfer
cycle
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
Bus release Bus release Bus
release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16-
bit, 2-state access space to external 16-bit, 2-state access space.