Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 268 of 980
REJ09B0050-0600
DMA
read
φ
Address bus
RD
LWR
TEND
HWR
Bus release Last transfer
cycle
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
Bus release Bus release Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.