Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 264 of 980
REJ09B0050-0600
Address T
B
Address B
B
Transfer
Address T
A
Address B
A
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Legend:
Address
Address
Address
Address
Where :
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (M·N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
T
A
T
B
B
A
B
B
L
A
L
B
N
M
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.