Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 260 of 980
REJ09B0050-0600
Address T
A
Address B
A
Transfer
Address T
B
Legend:
Address
Address
Address
Address
Where :
Address B
B
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
T
A
T
B
B
A
B
B
L
A
L
B
N
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends.
Figure 7.12 shows an example of the setting procedure for normal mode.