Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 245 of 980
REJ09B0050-0600
Transfer Mode Transfer Source Remarks
Short
address
mode
Single address mode
• 1-byte or 1-word transfer
for a single transfer
request
• 1-bus cycle transfer by
means of DACK pin
instead of using address
for specifying I/O
• Sequential mode, idle
mode, or repeat mode
can be specified
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception
complete interrupt
• A/D converter
conversion end
interrupt
• External request
• Up to 4 channels can
operate independently
• External request
applies to channel B
only
• Single address mode
applies to channel B
only
Normal mode
(1) Auto-request
• Transfer request is
internally held
• Number of transfers (1 to
65,536) is continuously
sent
• Burst/cycle steal transfer
can be selected
• Auto-request • Max. 2-channel
operation, combining
channels A and B
Full
address
mode
(2) External request
• 1-byte or 1-word transfer
for a single transfer
request
• Number of transfers: 1 to
65,536
• External request •
Block transfer mode
• Transfer of 1-block, size
selected for a single
transfer request
• Number of transfers: 1 to
65,536
• Source or destination can
be selected as block area
• Block size: 1 to 256 bytes
or word
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception
complete interrupt
• A/D converter
conversion end
interrupt
• External request
•