Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 244 of 980
REJ09B0050-0600
7.5 Operation
7.5.1 Transfer Modes
Table 7.4 lists the DMAC transfer modes.
Table 7.4 DMAC Transfer Modes
Transfer Mode Transfer Source Remarks
Short
address
mode
Dual address mode
• 1-byte or 1-word transfer
for a single transfer
request
• Specifies the transfer
destination/source
address and performs
transfer in 2 bus cycles
(1) Sequential mode
• Memory address
incremented or
decremented by 1 or 2
• Number of transfers: 1 to
65,536
(2) Idle mode
• Memory address fixed
• Number of transfers: 1 to
65,536
(3) Repeat mode
• 1-byte or 1-word transfer
for a single transfer
request
• Memory address
incremented or
decremented by 1 or 2
• Continues transfer after
sending number of
transfers (1 to 256) and
restoring the initial value
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception
complete interrupt
• A/D converter
conversion end
interrupt
• External request
• Up to 4 channels can
operate independently
• External request
applies to channel B
only
• Single address mode
applies to channel B
only