Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 240 of 980
REJ09B0050-0600
7.3.7 DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
In short address mode, the TEND pin is only available for channel B. The transfer end signal
indicates the transfer cycle in which the transfer counter has become 0 regardless of the transfer
source. Note however that the transfer end signal exceptionally indicates the transfer cycle in
which the block counter has become 0 in block transfer mode.
Bit Bit Name Initial Value R/W Description
7, 6 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
5 TEE1 0 R/W Transfer End Enable 1
Enables or disables transfer end pin 1
(TEND1) output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4 TEE0 0 R/W Transfer End Enable 0
Enables or disables transfer end pin 0
(TEND0) output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3
to
0
⎯ 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.