Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 237 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE1 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
When DTME0 is cleared to 0 while this bit is set
to 1, the DMAC regards this as indicating a
break in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE0 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.