Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 234 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
6 DTE1 0 R/W Data Transfer Enable 1
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and
the activation source is ignored. If the activation
source is an internal interrupt, an interrupt
request is issued to the CPU or DTC. If the
DTIE1 bit is set to 1 when DTE1 = 0, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to the
CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by
the activation source. When a request is issued
by the activation source, DMA transfer is
executed.
[Clearing conditions]
• When initialization is performed
• When the specified number of transfers have
been completed
• When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0