Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 225 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
• Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(for the first transfer after data transfer is
enabled, activated by DREQ pin low-level
input)
0011: Activated by DREQ pin low-level input
010×: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1×××: Setting prohibited
• Block Transfer Mode
0000: Setting prohibited
0001: Activated by A/D converter conversion
end interrupt
0010: Activated by DREQ pin falling edge input
(for the first transfer after data transfer is
enabled, activated by DREQ pin low-level
input)
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited