Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 224 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
10
to
8
⎯ All 0 R/W Reserved
Though these bits can be read from or written to,
the write value should always be 0.
Legend:
×: Don't care
• DMACR_0B and DMACR_1B
Bit Bit Name Initial Value R/W Description
7 ⎯ 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.
6
5
DAID
DAIDE
0
0
R/W
R/W
Destination Address Increment/Decrement
Destination Address Increment/Decrement
Enable
These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1
• When DTSZ = 1, MARB is incremented by 2
10: MARB is fixed
11: MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1
• When DTSZ = 1, MARB is decremented by 2
4 — 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor 3 to 0
These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.