Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 216 of 980
REJ09B0050-0600
• DMA control register_1B (DMACR_1B)
• DMA band control register H (DMABCRH)
• DMA band control register L (DMABCRL)
• DMA write enable register (DMAWER)
• DMA terminal control register (DMATCR)
The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.
Table 7.2 Short Address Mode and Full Address Mode (Channel 0)
FAE0 Description
0 Short address mode specified (channels 0A and 0B operate independently)
Channel 0A
MAR_0AH Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source
IOAR_0A
ETCR_0A
DMACR_0A
Channel 0B
MAR_0BH
MAR_0AL
MAR_0BL
IOAR_0B
ETCR_0B
DMACR_0B
1 Full address mode specified (channels 0A and 0B operate in combination as channel 0)
Channel 0
MAR_0AH Specifies transfer source address
Specifies transfer destination address
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
IOAR_0A
ETCR_0A
DMACR_0A
MAR_0BH
MAR_0AL
MAR_0BL
IOAR_0B
ETCR_0B
DMACR_0B