Datasheet

Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 215 of 980
REJ09B0050-0600
7.2 Input/Output Pins
Table 7.1 summarizes the pins of the interrupt controller.
Table 7.1 Pin Configuration
Channel Pin Name Symbol I/O Function
0 DMA request 0 DREQ0 Input Channel 0 external request
DMA transfer acknowledge 0 DACK0 Output Channel 0 single address
transfer acknowledge
DMA transfer end 0 TEND0 Output Channel 0 transfer end
1 DMA request 1 DREQ1 Input Channel 1 external request
DMA transfer acknowledge 1 DACK1 Output Channel 1 single address
transfer acknowledge
DMA transfer end 1 TEND1 Output Channel 1 transfer end
7.3 Register Descriptions
• Memory address register_0AH (MAR_0AH)
• Memory address register_0AL (MAR_0AL)
• I/O address register_0A (IOAR_0A)
• Transfer count register_0A (ECTR_0A)
• Memory address register_0BH (MAR_0BH)
• Memory address register_0BL (MAR_0BL)
• I/O address register_0B (IOAR_0B)
• Transfer count register_0B (ECTR_0B)
• Memory address register_1AH (MAR_1AH)
• Memory address register_1AL (MAR_1AL)
• I/O address register_1A (IOAR_1A)
• Transfer count register_1A (ETCR_1B)
• Memory address register_1BH (MAR_1BH)
• Memory address register_1BL (MAR_1BL)
• I/O address register_1B (IOAR_1B)
• Transfer count register_1B (ETCR_1B)
• DMA control register_0A (DMACR_0A)
• DMA control register_0B (DMACR_0B)
• DMA control register_1A (DMACR_1A)