Datasheet

Rev.6.00 Mar. 18, 2009 Page xxv of lviii
REJ09B0050-0600
6.11.1 Operation ............................................................................................................. 209
6.11.2 Bus Transfer Timing............................................................................................ 210
6.12 Bus Controller Operation in Reset .................................................................................... 211
6.13 Usage Notes ...................................................................................................................... 211
6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 211
6.13.2 External Bus Release Function and Software Standby ........................................ 211
6.13.3 External Bus Release Function and CBR Refreshing .......................................... 211
6.13.4 BREQO Output Timing ....................................................................................... 212
Section 7 DMA Controller (DMAC) ............................................................................. 213
7.1
Features ............................................................................................................................. 213
7.2 Input/Output Pins .............................................................................................................. 215
7.3 Register Descriptions ........................................................................................................ 215
7.3.1 Memory Address Registers (MARA and MARB)............................................... 217
7.3.2 I/O Address Registers (IOARA and IOARB) ...................................................... 217
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)................................... 218
7.3.4 DMA Control Registers (DMACRA and DMACRB) ......................................... 219
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 226
7.3.6 DMA Write Enable Register (DMAWER) .......................................................... 238
7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 240
7.4 Activation Sources ............................................................................................................ 241
7.4.1 Activation by Internal Interrupt Request.............................................................. 242
7.4.2 Activation by External Request ........................................................................... 242
7.4.3 Activation by Auto-Request................................................................................. 243
7.5 Operation........................................................................................................................... 244
7.5.1 Transfer Modes .................................................................................................... 244
7.5.2 Sequential Mode .................................................................................................. 246
7.5.3 Idle Mode............................................................................................................. 249
7.5.4 Repeat Mode ........................................................................................................ 252
7.5.5 Single Address Mode ........................................................................................... 256
7.5.6 Normal Mode....................................................................................................... 259
7.5.7 Block Transfer Mode ........................................................................................... 262
7.5.8 Basic Bus Cycles.................................................................................................. 267
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles ............................................... 267
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 275
7.5.11 Write Data Buffer Function ................................................................................. 281
7.5.12 Multi-Channel Operation ..................................................................................... 282
7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles ......... 283
7.5.14 DMAC and NMI Interrupts.................................................................................. 284
7.5.15 Forced Termination of DMAC Operation............................................................ 285