Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 208 of 980
REJ09B0050-0600
6.10.3 Transition Timing
Figure 6.56 shows the timing for transition to the bus released state.
CPU
cycle
External bus released state
External space
access cycle
T
1
T
2
φ
Address bus
HWR, LWR
BREQ
BACK
BREQO
High impedance
High impedance
High impedance
High impedance
High impedance
[1] [2] [3] [5][4] [6]
[7] [8]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Note: However that if BREQO is asserted by a CBR refresh request, BREQO signal is
kept low until a CBR refresh cycle starts.
Data bus
AS
RD
Figure 6.56 Bus Released State Transition Timing