Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 207 of 980
REJ09B0050-0600
(High) External bus release > External access by internal bus master (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)
6.10.2 Pin States in External Bus Released State
Table 6.9 shows pin states in the external bus released state.
Table 6.9 Pin States in Bus Released State
Pins Pin State
A23 to A0 High impedance
D15 to D0 High impedance
CSn (n = 7 to 0) High impedance
UCAS, LCAS High impedance
AS High impedance
RD High impedance
OE High impedance
HWR, LWR High impedance
DACKn (n = 1, 0) High