Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 206 of 980
REJ09B0050-0600
6.10 Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access. If any of the following requests are issued in the external bus released state, the BREQO
signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
6.10.1 Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters can perform accesses using the internal bus.
When an internal bus master wants to make an external access, it temporarily defers initiation of
the bus cycle, and waits for the bus request from the external bus master to be canceled. If a
refresh request is generated in the external bus released state, or if a SLEEP instruction is executed
to place the chip in software standby mode or all-module-clocks-stopped mode, refresh control
and software standby or all-module-clocks-stopped control is deferred until the bus request from
the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows: