Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 203 of 980
REJ09B0050-0600
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
DRAM space writeDRAM space read
T
c2
T
i
T
c1
RASn (CSn)
UCAS, LCAS
HWR
OE (RD)
Note: n = 2, 3
φ
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode