Datasheet
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 202 of 980
REJ09B0050-0600
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
0 — — — — Disabled
1 — — — 0 1 state inserted
Normal space read
1 2 states inserted
0 — — — — Disabled
1 — — — 0 1 state inserted
Normal space write
DRAM/ space read
1 2 states inserted
DRAM/ space write 0 — — — — Disabled
1 — — — 0 1 state inserted
Normal space read
1 2 states inserted
DRAM/ space read 0 — — — — Disabled
1 — — — 0 1 state inserted
1 2 states inserted
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/ space burst access. Figures 6.54 shows an
example of the timing for idle cycle insertion in the case of consecutive read and write accesses to
DRAM/continuous synchronous DRAM space.