Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 201 of 980
REJ09B0050-0600
Table 6.7 shows whether an idle cycle is inserted or not in mixed access to normal space and
DRAM.
Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
— 0 — — — Disabled
— 1 — — 0 1 state inserted
Normal space read
(different area)
1 2 states inserted
— 0 — — — Disabled
— 1 — — 0 1 state inserted
DRAM/ space read
1 2 states inserted
— — 0 — — Disabled
— — 1 — 0 1 state inserted
Normal space write
1 2 states inserted
— — 0 — — Disabled
— — 1 — 0 1 state inserted
Normal space read
DRAM/ space write
1 2 states inserted
DRAM/ space read
— 0 — — — Disabled
— 1 — 0 — Disabled
1 0 1 state inserted
Normal space read
1 2 states inserted
— 0 — — — Disabled
— 1 — 0 — Disabled
1 0 1 state inserted
DRAM/ space read
1 2 states inserted
— — 0 — — Disabled
— — 1 0 — Disabled
1 0 1 state inserted
Normal space write
1 2 states inserted
DRAM/ space write — — 0 — — Disabled
— — 1 0 — Disabled
1 0 1 state inserted
1 2 states inserted