Datasheet

Rev.6.00 Mar. 18, 2009 Page xxiv of lviii
REJ09B0050-0600
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 144
6.4 Operation .......................................................................................................................... 144
6.4.1 Area Division....................................................................................................... 144
6.4.2 Bus Specifications................................................................................................ 146
6.4.3 Memory Interfaces ............................................................................................... 148
6.4.4 Chip Select Signals .............................................................................................. 149
6.5 Basic Bus Interface ........................................................................................................... 150
6.5.1 Data Size and Data Alignment............................................................................. 150
6.5.2 Valid Strobes........................................................................................................ 152
6.5.3 Basic Timing........................................................................................................ 153
6.5.4 Wait Control ........................................................................................................ 161
6.5.5 Read Strobe (RD) Timing.................................................................................... 162
6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 163
6.6 DRAM Interface ............................................................................................................... 165
6.6.1 Setting DRAM Space........................................................................................... 165
6.6.2 Address Multiplexing........................................................................................... 165
6.6.3 Data Bus............................................................................................................... 166
6.6.4 Pins Used for DRAM Interface............................................................................ 167
6.6.5 Basic Timing........................................................................................................ 168
6.6.6 Column Address Output Cycle Control ............................................................... 169
6.6.7 Row Address Output State Control...................................................................... 170
6.6.8 Precharge State Control ....................................................................................... 172
6.6.9 Wait Control ........................................................................................................ 173
6.6.10 Byte Access Control ............................................................................................ 176
6.6.11 Burst Operation.................................................................................................... 177
6.6.12 Refresh Control.................................................................................................... 182
6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 187
6.7 Burst ROM Interface......................................................................................................... 190
6.7.1 Basic Timing........................................................................................................ 190
6.7.2 Wait Control ........................................................................................................ 192
6.7.3 Write Access ........................................................................................................ 192
6.8 Idle Cycle.......................................................................................................................... 193
6.8.1 Operation ............................................................................................................. 193
6.8.2 Pin States in Idle Cycle........................................................................................ 204
6.9 Write Data Buffer Function .............................................................................................. 204
6.10 Bus Release....................................................................................................................... 206
6.10.1 Operation ............................................................................................................. 206
6.10.2 Pin States in External Bus Released State............................................................ 207
6.10.3 Transition Timing ................................................................................................ 208
6.11 Bus Arbitration.................................................................................................................. 209