Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 198 of 980
REJ09B0050-0600
T
p
Address bus
φ
RD
RAS
HWR
UCAS, LCAS
External read
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space writeDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.51 and 6.52 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.