Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 197 of 980
REJ09B0050-0600
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.49 and 6.50.
T
p
Address bus
φ
RD
RAS
UCAS, LCAS
External read
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space readDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)