Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 196 of 980
REJ09B0050-0600
T
1
Address bus
φ
RD
Bus cycle A
T
2
T
3
T
1
T
2
Bus cycle B
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Address bus
Idle cycle
φ
Bus cycle A
T
2
T
3
T
i
T
1
Bus cycle B
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
2
CS (area A)
CS (area B)
RD
CS (area A)
CS (area B)
Figure 6.47 Relationship between Chip Select (CS) and Read (RD)
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a T
p
cycle is inserted, and a T
i
cycle is not. The
timing in this case is shown in figure 6.48.
T
1
Address bus
φ
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 6.48 Example of DRAM Full Access after External Read
(CAST = 0)