Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 195 of 980
REJ09B0050-0600
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output floating time
Data collision
(a) No idle cycle insertion
(ICIS2 = 0)
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
Bus cycle B
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
T
2
HWR
HWR, LWR
CS (area A)
CS (area B)
CS (area A)
CS (area B)
Idle cycle
T
i
Figure 6.46 Example of Idle Cycle Operation (Read after Write)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.47. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.