Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 191 of 980
REJ09B0050-0600
T
1
Upper address bus
Lower address bus
φ
CSn
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Note: n = 1, 0
Figure 6.42 Example of Burst ROM Access Timing
(ASTn = 1, 2-State Burst Cycle)
