Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 189 of 980
REJ09B0050-0600
When DDS = 0 : When DRAM space is accessed in DMAC single address transfer mode, full
access (normal access) is always performed. With the DRAM interface, the DACK output goes
low from the T
r
state.
In modes other than DMAC single address transfer mode, burst access can be used when
accessing DRAM space.
Figure 6.41 shows the DACK output timing for the DRAM interface when DDS = 0.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK
Address bus
T
r
T
c1
T
c2
Note: n = 2, 3
T
c3
Row address Column address
High
High
Figure 6.41 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)