Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 188 of 980
REJ09B0050-0600
When DDS = 1 : Burst access is performed by determining the address only, irrespective of the
bus master. With the DRAM interface, the DACK output goes low from the T
c1
state.
Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK
Address bus
T
r
T
c1
T
c2
Note: n = 2, 3
Row address Column address
High
High
Figure 6.40 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0)