Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 186 of 980
REJ09B0050-0600
T
Rp
φ
T
Rr
UCAS, LCAS
Software
standby
T
Rc3
HWR (WE)
CSn (RASn)
Note: n = 2, 3
High
Figure 6.38 Self-Refresh Timing
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.39 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.