Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 183 of 980
REJ09B0050-0600
RTCNT
N
RTCOR
N
H'00
Refresh request
signal and CMF bit
setting signal
Figure 6.34 Compare Match Timing
T
Rp
φ
CSn (RASn)
T
Rr
T
Rc1
T
Rc2
UCAS, LCAS
Note: n = 2, 3
Figure 6.35 CBR Refresh Timing
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.36 shows the timing when bits RCW1 and RCW0 are set.