Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 181 of 980
REJ09B0050-0600
• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.32 shows an example of
the timing in RAS up mode.
Normal space
read
DRAM space
read
T
p
T
r
T
c1
T
c2
T
c1
T
c2
DRAM space read
T
1
T
2
Note: n = 2, 3
φ
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Address bus
Row address Column address 1 Column address 2 External address
Figure 6.32 Example of Operation Timing in RAS Up Mode
(RAST = 0, CAST = 0)