Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 180 of 980
REJ09B0050-0600
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Normal space
read
DRAM space
read
T
p
T
r
T
c1
T
c2
T
1
T
2
DRAM space read
T
c1
T
c2
Note: n = 2, 3
φ
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Address bus
Row address Column address 1 Column address 2External address
Figure 6.31 Example of Operation Timing in RAS Down Mode
(RAST = 0, CAST = 0)